Computer Technology News & Tips

One of the ways to boost single-threaded performance on multicore machines is to shut down the cores that aren’t in use and divert power to whichever cores are running the single-threaded workload. That’s essentially what Intel’s Turbo Boost does—it can dynamically “overclock” one or more individual cores, based on the needs of the system and the amount of power and thermal headroom available.

This “brute force” approach is actually the opposite of making use of multicore—it’s about deliberately cutting back on the processor’s core count, in some cases all the way down to one active core, in exchange for a single-threaded boost. In short, it amounts to a temporary, strategic retreat from the multicore era.

Now AMD has revealed new details of how it plans to endow its multicore processors with the same dynamic power optimization capabilities, but (at least initially) via a much cruder implementation.

The new feature in AMD’s Phenom line of desktop processors is called Turbo CORE, and it will make its debut with the upcoming six-core Phenom II X6 (“Thuban”) line. Today, AMD gave the first details of Turbo CORE, and they are pretty straightforward.

When the processor’s power consumption drops below a certain level because three or more cores went idle, the chip downclocks the idle cores by a fixed amount and cranks up the power and clockspeed on the remaining cores by a fixed amount. So the chip is either in a turbo state or it’s running normally—there are only two options. And the idle cores don’t actually go into a sleep state—they’re just downclocked by a few hundred MHz.

Turbo CORE’s functionality is so basic that it appears that AMD really hasn’t put much effort into doing the necessary plumbing for more fine-grained power optimization—multiple power planes and extensive gating are needed to actually make this kind of strategy work to the degree that it does on the new Nehalems. Even so, Turbo CORE is better than nothing in this regard.

It’s a bit surprising that this new feature wasn’t included in the recent Magny-Cours processor. Servers need power optimization even more than desktops, although in the server space it’s more critical to underclock than it is to overclock (underutilization is a huge problem in datacenters). AMD has to be working on this for the next iteration of its Opteron line, though; I can’t imagine it going beyond 12 cores and not including such technology.

AMD hasn’t announced when it will actually launch the Phenom II X6; today’s reveal was just about Turbo CORE. Anandtech has an unofficial look at the likely launch lineup, if you’re dying to know right away. When the new chips do launch, though, they’ll be drop-in compatible with Socket AM2+ and AM3 boards—only a BIOS update is needed.

Source: Arstechnica

SAN FRANCISCO—The “Llano” processor that AMD described today in an ISSCC session is not a CPU, and it’s not a GPU—instead, it’s a hybrid design that the chipmaker is calling an “application processor unit,” or APU. Whatever you call it, it could well give Intel a run for its money in the laptop market, by combining a full DX11-compatible GPU with four out-of-order CPU cores on a single, 32nm processor die.

Details on the highly parallel vector hardware—the “GPU” part of the device—have yet to be disclosed, but AMD is focusing today’s revelations on the CPU part of the design. In a nutshell, AMD has taken the “STARS” core that’s used in their current 45nm offerings, shrunk it to a new 32nm SOI high-K process, and added new power gating and dynamic power optimization capabilities to it. Each out-of-order core has a bit under 35 million transistors, and a 1MB L2 cache that’s not included in that number. AMD is targeting sub-3GHz operation, and a power consumption range of 2.5 to 25 watts.

The chipmaker will put down four such cores, shown in the micrograph below, along with enough vector hardware to power a DX11 GPU. Overall, most of the work on the x86 side of Llano was done on dynamic power optimization and on fitting the design to the 32nm process.   In this respect, Llano differs from the upcoming “Bobcat” mobile part in that the latter is more portable across a range of processes and configurations, and features less custom work.

AMD has announced that Llano will be sampling in the second half of this year, and will be available from OEMs sometime in 2011.

Power optimization goes digital

It’s not often that I say this, but perhaps the most interesting and novel part of the Llano core is its unique approach to dynamic power optimization. AMD fellow Sam Naffziger walked me through the approach in a briefing this morning, and it departs from traditional power management approaches in that it relies on digital, not analog, data.

A normal processor power module takes analog input from a set of diodes placed throughout the die, and these diodes act as thermal sensors, informing the module when the die heats up in an area due to increased compute activity. In this model, then, die temperature is monitored as a proxy for power consumption, and the power module uses this temperature/power data to make on-the-fly adjustments to parameters like clockspeed. The blessing and curse of this method is that these analog sensors respond to every change in thermals, whether it’s driven by an actual, compute-related boost in power consumption or by external, environmental factors, like a sudden rise in ambient temperature.

Llano’s approach, in contrast, uses a set of 95 digital signals from different parts of the chip that AMD has empirically identified as having a strong correlation to power consumption. So signals like integer traffic, cache misses, or branch mispredicts are monitored via low-frequency sampling, and these signals give the power module a picture of the chip’s power consumption that AMD claims “is accurate to within 2 percent across a broad range of application types.”

High hopes for first genuine “Fusion” offspring of AMD + ATI

I personally have relatively high hopes for Llano as notebook part that could well out-do whatever Intel has in 2011. Intel is infamous for the poor quality of its integrated graphics processors (IGPs), and, while the most recent Intel IGPs are much less embarrassing than their predecessors, it’s not clear that the company has the ability or the will to compete with NVIDIA and AMD/ATI in this area. So when it comes to raw performance as a CPU and GPU, I expect Llano to do quite well. But for commercial success as a mobile part, the big question concerns Llano’s platform-level power draw, and that will depend on real-world success of the power management innovations that AMD has introduced today.

It’s possible that, for gaming on-the-go, Llano’s biggest competitor will be NVIDIA’s upcoming x86 CPU + GPU combination. But right now, that device is still just a secret skunkworks project about which almost nothing is known. Still, if it’s not public by 2011, I’m not sure what NVIDIA’s mobile strategy will look like. With CPU/GPU fusion products like Llano and the DMI licensing dispute combining to kill NVIDIA’s IGP business, the company needs new mobile ideas in a big way.

Source: arstechnica.com

PCOnline, a Chinese hardware enthusiast site, has revealed some exciting new information regarding Intel’s up and coming 32nm Gulftown chip that’s expected to make the rounds Q1 of 2010.

Buffing a whopping 6 cores and 12 threads, 12MB of Intel Smart Cache, Intel Hyper-Threading technology and Intel Turbo Boost technology, the 980X is definitely an exciting way to kick off the new year in tech.

core i7

Source: geeksmack.net